The invention relates to a method of fabricating a flash memory device and, more particularly, to a method of fabricating a flash memory device that reduces disturbance between gates.
A flash memory device includes a cell region including a memory cell, and a peripheral (“peri”) region including transistors for transferring a driving voltage. The cell region is described in detail below.
The cell region comprises strings having a plurality of memory cells connected in series. Each string includes a plurality of memory cells and a select transistor formed at both ends of the string. The memory cell has a structure in which a tunnel insulating film, a floating gate, a dielectric layer, and a control gate are sequentially laminated over a semiconductor substrate. Meanwhile, the select transistor has the same structure as that of the memory cell, but has a floating gate and a control gate in contact with each other through a contact hole formed in the dielectric layer.
Memory cells included in different strings share word lines and are connected to each other, and they are operated in response to voltage applied to the word lines. Select transistors included in different strings are connected through a select line and are operated in response to voltage applied to the select line.
In particular, in the case of a NAND flash memory device, as the level of integration increases, the distance between memory cells narrows. Thus, an interference phenomenon may occur between adjacent memory cells. The interference phenomenon is generally generated between adjacent floating gates and may also be generated due to an increased capacitance between the floating gates.
When a program operation in a flash memory device is performed, a program disturbance characteristic may be degraded. This is described in more detail below.
The program operation is performed by applying a program voltage to a selected word line in order to inject electrons into the floating gate of a selected memory cell. However, since a plurality of memory cells are connected to the word line, the program operation may be performed even on the memory cells on which the program operation should not be performed. To prevent this problem, channel boosting is generated in strings on which the program operation should not be performed so as to prevent electrons from being introduced to the floating gate.
Upon channel boosting, a junction region between the source select transistor and an adjacent memory cell is boosted to a specific voltage (for example, 8V) and a gate of the source transistor is grounded. In this condition, a gate induced drain leakage (GIDL) may be generated at a portion where the source select transistor and the junction overlap each other. Of an electron-hole pair generated in the junction, electrons can rapidly migrate to a channel region to which a high bias is applied. This degrades a program disturbance characteristic. In particular, this phenomenon is very pronounced between the select transistor and an adjacent memory cell.